1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the present invention relates to the structure of non-volatile memory cells permitting electrically writing and erasing information, which is referred as an electrically erasable and programmable read only memory (EEPROM).
2. Description of the Prior Art
FIGS. 1A to 1C show the structure of an existing semiconductor memory of a floating-gate type. FIG. 1A is a plan view depicting the arrangement of the semiconductor memory cell, FIG. 1B shows a cross sectional structure taken along the line A-A' in FIG. 1A, and FIG. 1C shows a cross sectional structure taken along the line B-B'. The structure of the existing semiconductor memory cell, with reference to FIGS. 1A to 1C is described below.
The semiconductor memory cell comprises a sense transistor and a select transistor. Both transistors are provided on the main surface of a silicon semiconductor substrate 11.
The sense transistor comprises a drain region 8 and a source region 9 which are formed through diffusion of impurities on the main surface of the semiconductor substrate 11, a thin tunnel-oxide film 6 formed in a predetermined area on the drain region 8, a floating gate 2 made of polysilicon and formed through a dielectric film on the semiconductor substrate 11 at the area including at least the tunnel-oxide film 6, and a control gate 1 formed through a dielectric film on the floating gate 2. The control gate 1 and the floating gate 2 form a capacitor in the area where the two gates are overlapped with an insulating film (an interlayer insulating film) serving as a dielectric. With the tunnel-oxide film 6 serving as a dielectric, the floating gate 2 and the drain region 8 form a capacitor. In the area excluding the tunnel-oxide film 6, there exists a capacitance formed by the floating gate 2 and the semiconductor substrate 11, with the gate-oxide film 10 serving as a dielectric. The floating gate 2 stores electric charges and causes the emission or injection of electron charges from or into the drain region 8 through the tunnel-oxide film 6 as a function of the voltage applied between the control gate 1 and the drain region 8.
The select transistor comprises a source region 8 and a drain region 12 which are formed through diffusion of impurities onto the main surface of the semiconductor substrate 11 and the gate region 3 which receives a select signal. The drain region 12 is connected to an aluminium interconnection 4 through a contact hole 5. The aluminium interconnection 4 forms a bit line, while the gate region 3 forms a word line. In the following description the gate region 3 is described as a word line 3, while the aluminium interconnection 4 is described as a bit line 4.
According to the arrangement illustrated in FIGS. 1A and 1B, the sense transistor has a gate region 7, which is formed by the floating gate 2 in the region where no tunnel-oxide film 6 exits. In the gate region 7, as shown in FIG. 1A, the bit line 4, the control 1 and the floating gate 2 overlap each other through the respective dielectric films. The select transistor is either on or off in response to signals which are sent respectively through the word line 3 and the bit line 4 and then the transistor senses the information provided by the connected sense transistor. Further, it is electrically insulated from the adjacent cells by the cell isolation region 10 (a field oxide).
FIG. 2 shows an equivalent circuit diagram of a semiconductor memory cell which is illustrated in FIG. 1A to 1C. As shown in FIG. 2, the drain of the sense transistor and the source of the select transistor are formed in the same diffusion layer 8 and connected to each other.
In the sense transistor, as described above, the control gate 1, the floating gate 2 and the semiconductor substrate 11 are formed through the respective dielectric layers. Thus, a capacitance is formed between them and a capacitance network is composed thereby.
FIG. 3 shows an equivalent circuit diagram of the capacitance network. As shown in FIG. 3, the capacitance network comprises a capacitance 14 composed of the control gate 1, the interlayer dielectric, and the floating gate 2; a capacitance 13 formed of the floating gate 2, the tunnel-oxide film, and the drain region 8; and a capacitance 15 formed between the floating gate 2 and the semiconductor substrate 11, minus the capacitance 12. The capacitances 13 and 15 are electrically connected in parallel and the capacitor 14 is electrically connected in series with those parallel connected capacitors (13 and 15). Now a description will be made of the operation with reference to FIGS. 1A to 1C, 2 and 3.
A memory cell of this floating-gate type stores information depending on the state of the excessive storage of electrons on the floating gate 2 or the state existence of the apparently positive electric charges due to electron insufficiency thereon. The operation of injecting electrons into the floating gate 2 is performed in the following manner. First a programming voltage V.sub.PP is applied to the word line 3 and the control gate 1. The source 9 of the sense transistor and the bit line 4 are set to a ground potential (0V). At this time an inversion layer is formed on the surface of the semiconductor substrate beneath the word line 3 and the potential of the drain region 8 of the sense transistor, i.e. the source region of the sense transistor, has the same ground potential (0V) as that of the bit line 4 through the drain 12 on the inversion layer and the select transistor,
FIG. 4 shows an equivalent circuit diagram of the capacitance network implemented by a sense transistor in injecting electrons into the floating gate.
As shown in FIG. 4, the programming voltage V.sub.PP is applied to the control gate 1, and the source region 9 and the drain region 8 are grounded. At this time the semiconductor substrate 11 is normally grounded. Q.sub.F is the electric charge stored at the floating gate 2 and the voltage V.sub.F is a voltage to be applied to the capacitance 13, which is formed by the floating gate 2, the tunneloxide film 6 and the drain region 8.
Assuming that the capacitance value of the capacitance 13 is C.sub.1, the capacitance value of the capacitance 14 is C.sub.2, and the capacitance value of the capacitance 15 is C.sub.3, then the voltage V.sub.F is expressed as follows: EQU V.sub.F =(C.sub.2 V.sub.PP -Q.sub.F)/C.sub.T ( 1)
where C.sub.T =C.sub.1 +C.sub.2 +C.sub.3.
The voltage V.sub.F expressed by the above described equation (1) is applied across the thin tunnel-oxide film 6. Thus a high electric field is applied and the electrons existing in the drain region 8 flow as a Fowler-Nordheim-type tunnel current through the 10 tunnel-oxide film 6 and they are stored in the floating gate 2.
On the other hand, then electrons are removed from the floating gate 2, the programming voltage V.sub.PP is applied to the word line 3 and the bit line 4, and the control gate 1 is used an a ground potential (0V). Further the source region 9 of the sense transistor is electrically placed in a floating state to keep the electrons from leaking.
In this state the select transistor is placed in a conduction state and the potential of the drain region 8, i.e. the source of the select transistor, in the sense transistor is approximately the same as the potential V.sub.PP of the bit line 4.
FIG. 5 shows an equivalent circuit diagram of the capacitance network which is implemented by a sense transistor in drawing electrons out of the floating gate. Since the semiconductor substrate 11 is grounded, as shown in FIG. 5, the source region 9 in an electrically floating state is also grounded through the semiconductor substrate 11. Further the drain region 8 is supplied with the programming voltage V.sub.PP. Since the semiconductor substrate 11 is grounded, the junction capacitance formed between the drain region 8 and the substrate 11 contributes to the capacitance value of the capacitance 15. As a result, the capacitance becomes C.sub.3 '. However, a junction capacitance is as small as an amount nearly equal to the capacitance C.sub.3 in case of electron injection operation. In this state, the voltage V.sub.F applied to the capacitance 13 is expressed as follows: EQU V.sub.F ={(C.sub.2 +C.sub.3 ') V.sub.PP -Q.sub.F }/(C.sub.1 +C.sub.2 +C.sub.3 ') (2)
Since the voltage V.sub.F in the above described equation (2) make a high electric field accross the tunnel-oxide film 6, electrons in the floating gate 2 flows into the drain region 8 as Fowler-Nordheim-type tunnel current through the tunnel-oxide film region 6. Thus, the electrons in the floating gate 2 are deficient.
When excessive electrons exist in the floating gate 2, the threshold voltage of the sense transistor increases and, as a result, the sense current through the select transistor decreases. To the contrary, when the electrons in the floating gate 2 are deficient, the threshold voltage of the sense transistor decreases and, as a result, the sense current through the select transistor increases. The magnitude of this current is stored in the form of the logics "0" and "1" of the digital information.
The voltage V.sub.F applied to the tunnel-oxide film 6 can be increased by increasing the capacitance value C.sub.2 of the capacitance 14, as shown in the above described expression, provided that the programming voltage V.sub.PP is fixed. Higher voltage V.sub.F is not applicable because it causes the dielectric breakdown at the tunneling-oxide film 6. Contrarily, when lower voltage V.sub.F is applied, the tunnel current does not flow. In other words, an optimal value of the voltage V.sub.F exists Practically, the optimal value of the voltage V.sub.F is realized by proper selection of the values of the capacitance C.sub.2 and the programming voltage V.sub.PP.
The conventional semiconductor memory cells are structured as described above. In order to increase the capacitance C.sub.2, therefore, it was necessary to enlarge the overlapping area of the floating gate 2 and the control gate 1, or to decrease the thickness of the interlayer dielectric film between the floating gate 2 and the control gate 1. When the thickness of the interlayer dielectric film between the control gate 1 and the floating gate 2 is decreased, the reliability of the memory is reduced. The reason will be described in the following. Since this interlayer dielectric film is generally formed through thermal oxidation of the polysilicon constituting the floating gate, the decreased thickness of the interlayer dielectric film causes concentrated effect of the electric field, which are caused by the irregularity of the polysilicon surface, and furthermore the retention property of stored electric charges is deteriorated, while the dielectric resistance is considerably reduced. When the overlapping area of the control gate 1 and the floating gate 2 is increased (instead of a decreased thickness of the interlayer dielectric field), the increase of the overlapping area runs counter to enhancement of the degree of integration of the semiconductor memory cells. Thus, the above described defects were involved in the conventional semiconductor memory devices.
The following are the references citable as the prior art of the interest to the present invention.
(1) Jimmy Lee and Vinod K. Dham, "Design Consideration for Scaling Flotox E.sup.2 PROM Cell", IEEE IEDM 83, pp. 589-592, 1983.
(2) Bruce Euzent et al., "Reliability, Aspects of a Floating Gate E.sup.2 PROM", IEEE/PROC. IRPS. pp. 11-16,1981
(3) R. Cuppens et al., "An EEPROM for Microprocessors and Custom Logic", IEEE ISSCC Dig. Tech. Papers, pp. 268-269, February 24, 1984.
The above described Prior Art (1) discloses that the area of the tunnel-oxide should be considerably reduced in order to scale FLOTOX Cells without degrading the reliability.
The above described Prior Art (2) discusses the failure in mechanism of EEPROM for both erase and write cycling and data retention.
The above described Prior Art (3) reports that FLOTOX E.sup.2 PROM, with a signal polysilicon layer is accomplished by substituting a control gate with a diffusion layer.